/*
* Fake AD to simulate AD behaviour
*/
`timescale 1ns/1ps

module AD_DUMMY(
    input           clk,
    input           rst,
    output reg [31:0]   ad_data_o,
    output reg         ad_data_valid_o,
    input           ad_acquisition_en_i
);

  localparam       TCQ = 1;  // Clock-to-out delay

always @(posedge clk ) begin
    if ( rst ) begin
        ad_data_o       <= #TCQ 32'd0;
        ad_data_valid_o <= #TCQ 1'b0;
    end else begin
        if ( ad_acquisition_en_i ) begin
            ad_data_valid_o <= #TCQ 1'b1;
            ad_data_o       <= #TCQ ad_data_o + 32'd1;
        end else begin
            ad_data_valid_o <= #TCQ 1'b0;
            ad_data_o       <= #TCQ 32'd0;
        end
    end
end

endmodule

